1/4 rev. a structure silicon monolithic integrated circuit product power management lsi for multimedia lsi on cellular type bh6176gu functions ? 1ch 500ma, high efficiency step-down conv erter. (16 steps adjustable vo by i 2 c) ? 5-channel cmos-type ldos. (16 steps adjustable vo by i 2 c, 150ma 3, 300ma 2) ? ldo and stepdown converter power on/off control enabled by i2c interface or external pin ?i 2 c compatible interface. (device address is ?1001111?) ? wafer level csp package(2.6mm 2.6mm) for space-constrained applications. absolute maxi mum ratings ta = 2 5 ?c parameter symbol rating unit maximum supply voltage (vbat, pbat) vbatmax 6.0 v maximum supply voltage (vusb) vusbmax 6.0 v maximum supply voltage (dvdd) dvddmax 4.5 v maximum input voltage 1 (lx, fb, out1, out2, out3, out4, out5, out6, en_ld1, en_ld2, en_ld3, en_ld4) vinmax1 vbat + 0.3 v maximum input voltage 2 (nrst, clk, data) vinmax2 dvdd + 0.3 v power dissipation pd 900* 1 mw operating temperatur e range topr -35 +85 storage temperature range tstg -55 +125 *1 this is the allowable loss of when it is mounted on a rohm specification board 60mm 60mm. to use at temperature higher than 25 ? c , derate 1% per 1 ?c. recommended operating conditions (ta=25 ?c) parameter symbol range unit vbat, pbat voltage vbat * 2 2.20 5.50 v vusb voltage vusb * 2 2.20 5.50 v dvdd voltage vdvdd * 3 1.70 4.20 v *2 whenever the vbat or pbat or vusb voltage is under the ldo, swreg output voltage, the ldo and swreg output is not guaranteed to meet its published specifications. *3 the dvdd voltage must be under the battery voltage vbat, pbat at any times.
2/4 rev. a overview dimensions (vcsp85h2) ball descriptions block diagram swreg 0.8-2.40v pbat fb pgnd lx ldo1 1.00-3.30v 16 step ldo2 1.00-3.30v 16 step ldo3 1.20-3.30v 16 step ldo4 1.20-3.30v 16 step ldo5 1.20-3.30v 16 step out1 out2 out3 out4 out5 150ma 300ma 300ma 150ma 150ma 500ma ref refc en_ld1 en_ld2 en_ld3 en_ld4 i2c if data clk nrst dvdd init 1.00v init 1.00v init 2.60v init 2.80v init 1.80v init 3.30v vusb test ldo6 1.20-3.30v 16 step out6 300ma init 2.85v tsd ball no. pin name b4 data c4 clk e1 vbat1 e4 vbat2 a5 pbat a4 lx a3 pgnd b5 fb d4 nrst d5 out1 d1 out2 e5 out3 e3 out4 a1 out5 b1 refc c2 en_ld1 d2 en_ld2 d3 en_ld3 c3 en_ld4 a2 vusb c5 dvdd c1 gnd b3 test e2 out6 vbga080v050 (unit:mm) bh6176 lot
3/4 rev. a electrical characteristics (unl ess otherwise specified, ta=25 ? c, vbat, pbat=3.6 , vusb=5.0v) parameter symbol min. typ. max. unit condition circuit current circuit current 1 (off) iq1 - 0.4 1 a ldo1~6=off, swreg1=off, nrst=l, dvdd=0v circuit current 2 (standby) iq2 - 0.7 1.4 a ldo1~6=off, swreg1=off, nrst=h, dvdd=2.6v circuit current 3 (active) iq3 - 220 380 a ldo1~6=on (no load, initial voltage) swreg1=on (no load, initial voltage) nrst=h, dvdd=2.6v vusb=vbat external connection electrical characteristics (unl ess otherwise specified, ta=25 ? c, vbat, pbat=3.6 , vusb=5.0v) parameter symbol min. typ. max. unit condition logic pin character nrst (cmos input) input high level vih1 dvdd* 0.7 - dvdd+ 0.3 v pin voltage: dvdd input low level vil1 -0.3 - dvdd* 0.3 v pin voltage: 0 v logic input current iic1 0 0.3 1 a en_ld1, en_ld2, en_ld3, en_ld4 (nmos input) input high level vih2 1.44 - - v input low level vil2 - - 0.4 v logic input current iic2 -1 0 1 a clk, data (cmos input) input high level vih3 dvdd* 0.8 - dvdd+ 0.3 v input low level vil3 -0.3 - dvdd* 0.2 v logic input current iic3 -1 0 1 a data (cmos input) output low level vol - - 0.4 v iol=6ma swreg swreg output voltage vosw 0.94 1.00 1.06 v initial value, io=100ma ldos ldo1 output voltage vom1 0.97 1.000 1.030 v initial value io=1ma@vbat=4.5v io=150ma@vbat=3.4v ldo2 output voltage vom2 2.522 2.600 2.678 v initial value io=1ma@vbat=4.5v io=150ma@vbat=3.4v ldo3 output voltage vom3 2.716 2.800 2.884 v initial value io=1ma@vbat=4.5v io=300ma@vbat=3.4v ldo4 output voltage vom4 1.746 1.800 1.854 v initial value io=1ma@vbat=4.5v io=300ma@vbat=3.4v ldo5 output voltage vom5 3.201 3.300 3.399 v initial value io=1ma@vusb=5.5v io=150ma@vusb=4.4v ldo6 output voltage vom6 2.765 2.85 2.936 v initial value io=1ma@vbat=4.5v io=300ma@vbat=3.4v
4/4 rev. a use-related cautions (1) absolute maximum ratings if applied voltage (vbat, vadp, vusb), operating temperature range (topr), or other absolute maxi mum ratings are exceeded, ther e is a risk of damage. since it is not possible to identify short, open, or other damage modes , if special modes in which absolute ma ximum ratings are exceeded are assumed, consider applying fu ses or other physical safety measures. (2) recommended operating range this is the range within which it is possible to obtain roughly t he expected characteristics. for electrical characteristics, it is those that are guaranteed under the conditions for each parameter. even when t hese are within the recommended operating range, voltage and temperature characteristics are indicated. (3) reverse connection of power supply connector there is a risk of damaging the lsi by reve rse connection of the power supply connector. for protection from reverse connectio n, take measures such as externally plac ing a diode between the power supply and the power supply pin of the lsi. (4) power supply lines in the design of the board pattern, make power supply and gnd line wiring low impedance. when doing so, although the digital power suppl y and analog power supply are the same potential, separate the digital power sup ply pattern and analog power supply pattern to deter digital noise from entering the analog power supply due to the common impedanc e of the wiring patterns. similarly take pattern des ign into account for gnd lines as well. furthermore, for all power supply pins of the lsi, in conjunction with inserting ca pacitors between power supply and gnd pins, when using electrolytic capacitors, determine constants upon adequately confirming that capacitance loss occurring at low temperatures is not a problem for various characteristics of the capacitors used. (5) gnd voltage make the potential of a gnd pin such that it will be the lowest potential even if operating below that. in addition, confirm t hat there are no pins for which the potential becomes less than a gnd by actually including transition phenomena. (6) shorts between pins and misinstallation when installing in the set board, pay adequate attention to orientation and placement discrepancies of the lsi. if it is installed erroneously, there is a risk of lsi damage. ther e also is a risk of damage if it is shorted by a foreign substance getting between pins or between a pin and a power supply or gnd. (7) operation in strong magnetic fields be careful when using the lsi in a strong magnetic field, since it may malfunction. (8) inspection in set board when inspecting the lsi in the set board, si nce there is a risk of stress to the lsi when capacitors are connected to low impedance lsi pins, be sure to discharge for each process. moreover, when getti ng it on and off of a jig in the inspection process, always c onnect it after turning off the power supply, perform the inspection, and remove it after turning off the power supply. furthermore, as counte rmeasures against static electricity, use grounding in the assembly pr ocess and take appropriate care in transport and storage. (9) input pins parasitic elements inevitably are formed on an lsi structure due to potential relationships. because parasitic elements operat e, they give rise to interference with circuit oper ation and may be the cause of malfunctions as well as damage. accordingly, take car e not to apply a lower voltage than gnd to an input pin or use the lsi in other ways such that parasitic elements operate. moreover, do not a pply a voltage to an input pin when the power supply voltage is not being applied to the lsi. furthermore, when the power supply voltage is b eing applied, make each input pin a voltage less than the power supply voltage as well as within the guaranteed va lues of electrical characte ristics. (10) ground wiring pattern when there is a small signal gnd and a large current gnd, it is recommended that you separate the large current gnd pattern and small signal gnd pattern and provide single point grounding at the reference point of the set so that voltage variation due to resist ance components of the pattern wiring and large currents do not cause the small signal gnd voltage to change. take care that the gnd wiring pa ttern of externally attached components also does not change. (11) externally attached capacitors when using ceramic cap acitors for external ly attached capacitors, determine constant s upon taking into account a lowering of th e rated capacitance due to dc bias and capacitance change due to factors such as temperature. (12) thermal shutdown circuit (tsd) when the junction temperature becomes 160c (typ) or higher, the thermal shutdown circuit operates and turns the switch off. the thermal shutdown circuit, which is aimed at isolating the lsi from thermal runaway as much as possible, is not aimed at the protection or guarantee of the lsi. therefore, do not continuously use the lsi with this circuit operating or use the lsi assuming its op eration. (13) thermal design perform thermal design in which there are adequate margins by ta king into account the permissible dissipation (pd) in actual st ates of use. (14) rush current extra care must be taken on power coupling, power, ground line impedance, and pcb design while excess amount of rush current mi ght instantly flow through the power line when powering-up a lsi which is equipped with several power supplies, depending on on/off sequence and ramp delays.
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